How To Deliver Next-level Functional Safety For Modern Automotive Applications
The automotive industry today stands on the verge of a new era of car safety. Using autonomous driving technologies, automakers may soon eliminate accidents caused by human error.
Q
How many auto-related injuries take place in a year?
The Challenge: Autonomous Vehicle Safety
Under The Hood Of AURIX
What is the checker core?
The Solution
Q
How big of a factor does human error play in car accidents?
Getting To Know The AURIX Family
AURIX: At The Cutting Edge Of Automotive Tech
Safety
Performance
Networking
Scalability
Security
Enablement
Conclusion
Interested in learning more?
Contact Infineon Today
Safety
• Innovative multicore safety techniques,
with integrated checker core.
• Safe Peripherals, busses, memories, I/O
and a Safety Management Unit (SMU)
• Support for the ISO 26262 functional
safety standard.
• Meets the most rigorous safety level of
ISO 26262 ASIL-D & IEC61508 SIL-3
• Multicore technology.
• Processor performance as high as
1300 DMips.
• Up to three 300Mhz TriCore processors.
• As much as 8MB flash memory.
Performance
• Up to 2.7MB SRAM.
• Ethernet.
• High-speed serial link.
• CAN with Flexible Data Rate.
Networking
• Various multicore configurations,
ranging from 1 to 3 TriCore processors.
• Clock speeds spanning 133MHz to 300MHz.
• Flash memory density from 512kB to 8MB.
• Pinout compatibility among different
members of the family.
Scalability
• Various package options.
According to a 2015
fact sheet from the National Highway Traffic Safety Administration,
94 percent of all car mishaps are attributed to human error.
2.4M
According to a 2016 report published by the US Department of Transportation, there were 2.4 million auto-related injuries in 2015 in the United States alone.
Back
• Hardware Security Module (HSM)
Security
> Second-generation, hardware-supported
security functions.
> Capable to achieve medium Evita with
Symmetric Crypto (HW)
> Fully programmable security hardware.
> Supports Authentication and Encryption
• Expert tools.
Enablement
• Free tool chain.
• Technical experts.
• Reference designs.
• Preferred Design House support.
1
2
3
The checker core is an
on-chip processor that uses redundancy to ensure the accuracy of results generated by the chip’s main processor. If a discrepancy is detected, the checker core signals the safety management unit to warn about the issue.
The checker core delivers diversity, crunching code using different processing methods than the main processor and with 2 clocks delay in time to avoid common cause errors.
The incorporation of the checker core also saves time, cost and effort by eliminating the need to develop custom hardware and software solutions for verifying results.
What is the checker core?
Cores:
Hardware Security Module:
Flash Memory:
Clock Rate:
Cores:
Hardware Security Module:
Flash Memory:
Clock Rate:
2 TriCore Processor Cores, 2 Checker Cores
Optional
200 MHz
Up to 4 MB
3 TriCore Processor Cores, 1 Checker Core
Yes
Up to 8 MB
300 MHz
Cores:
Hardware Security Module:
Flash Memory:
Clock Rate:
2 TriCore Processor Cores, 1 Checker Core
No
Up to 2.5 MB
200 MHz
Cores:
Hardware Security Module:
Flash Memory:
Clock Rate:
1 TriCore Processor Core, 1 Checker Core
Optional
Up to 2 MB
200 MHz
Cores:
Hardware Security Module:
Flash Memory:
Clock Rate:
1 TriCore Processor Core, 1 Checker Core
No
Up to 1 MB
133 MHz
Cores:
Hardware Security Module:
Flash Memory:
Clock Rate:
1 TriCore Processor Core, 1 Checker Core
No
Up to 512 MB
133 MHz
TM
TM
TM
TM
TM
TM
TM
TM